Would this potentially ruin flicker effects programmed around the timing of the original signal?
Happily, it would have zero effect on that. Internally, all the timing for horizontal and vertical interrupts is completely regular. It's only when H and V sync get combined into C sync at the output stage that things get funky.
This is what the PCE's internal sync signals look like when recorded by a logic analyzer. You've got separate H and V sync, then the combined C sync at the bottom that gets mixed with composite video pretty much as-is. Bearing in mind that it's falling edges that the TV counts, compare the number of falling edges in the H sync line to the C sync line. C sync is missing one pulse at the end of the long V sync period.
TVs built to accept broadcast signals sent out over the airwaves have a robust error-correction circuit for sync called AFC, or automatic frequency control. It's primarily to prevent interference from triggering a horizontal refresh at the wrong time, but some older game consoles (and VCRs, too) rely on AFC to fix quirks in the sync signal timing.
Without it, you get this. I took this picture myself of a PCE running on an Ikegami studio master monitor built after 2000:
But again, this is just because of the weird way that the system combines the H and V sync pulses. To the software and even the part of the video processor that draws the picture itself, it's completely invisible.
If you really want to get crazy, the NES and SNES usually draw one horizontal line in 1364 ticks of the 21MHz master clock, but there is one line near the top of the screen that alternates between 1364 ticks and 1360 ticks in length every other frame. Apparently it was made this way to reduce dot-crawl, but it can cause a tiny amount of jitter in the top few displayed lines on very sensitive displays that aren't built with strong AFC.
The crazy thing is, it's not just an early pulse; the processing time for that horizontal line itself is 4 ticks short, too. There's no way to turn it off, but a guy over on the shmups.com forums has come up with a very interesting fix that works in both systems: with an FPGA, he basically cuts off the master clock signal and halts the entire system for 4 ticks every time that short line gets drawn. The system can't even tell the difference.
